1. Field of the Invention
The present invention generally relates to virtual multiple-read port memory arrays and, more particularly, to a circuit and method for effectively providing multiple read ports for a memory array composed of single-read port memory cells.
2. Background Description
In an M-row by N-bit memory array, with P data outputs, multiple reads per cycle are generally accomplished by using memory cells which have multiple read ports; i.e., P read ports per cell. This is necessary for full random access reading. In cases where full random access is not required, the additional read ports in each cell become redundant, wasting valuable device area. Moreover, with the push to fabricate higher density memory arrays, multiple read ports consume valuable silicon real estate. What is needed is the higher densities allowed by single read port memory arrays but with the capability of multiple simultaneous reads.